Retro Video Games and Consoles
Megalong Games > Xbox 360
The Xbox 360 is Microsoft's successor to their Xbox video game console, referred to during development as "Project Xenon", "Xbox 2", or "Xbox Next". The console was released on November 22, 2005 in North America, and will be released on December 2 in Europe, December 10 in Japan, March 23, 2006 in Australia and elsewhere in early 2006. The Xbox 360 will compete against the upcoming generation of consoles, including the Sony PlayStation 3 and Nintendo Revolution, and was officially unveiled on MTV on May 12, 2005, a week before E?.
In most countries the console is sold in two different configurations: the "Xbox 360" and the "Xbox 360 Core System". The Xbox 360 configuration, often referred to as the "Premium Edition", includes a hard drive (needed to play original Xbox games), wireless controller, headset, ethernet cable, Xbox Live silver subscription, and a componet HD AV cable.
The console hardware is based on a custom IBM PowerPC-based "Xenon" central processing unit (CPU) and a custom ATI R500-based "Xenos" graphics processing unit (GPU). It is equipped with 512 MB of RAM and uses the DVD-ROM storage medium for Xbox 360 game software.
The central processing unit (CPU), named Xenon, is a custom IBM triple-core PowerPC-based design.
* 90 nm process, 165 million transistors
* Three symmetrical cores, each one SMT-capable and clocked at 3.2 GHz
* One VMX-128 (IBM's branding for AltiVec) SIMD unit per core
* 128?128 register file for each VMX unit
* 1 MiB L2 cache (lockable by the GPU)
The graphics processing unit (GPU) is a custom ATI R500-based "Xenos"
* 337 million transistors total
* 500 MHz parent GPU (90 nm process, 232 million transistors)
* 500 MHz 10 MB daughter embedded DRAM framebuffer (90 nm process, 105 million transistors)
o NEC designed eDRAM has internal logic for color, alpha blending, Z/stencil buffering, and anti-aliasing.
* 48-way parallel floating-point dynamically-scheduled shader pipelines
o 4 arithmetic logic units per pipe for vertex or pixel shader processing
o Unified shader architecture (This means that each pipeline is capable of running either pixel or vertex shaders.)
o Support for DirectX 9.0 Shader Model 3.0, limited support for future DirectX 10 shader models
o 2 Shader operations per pipe per cycle
o 96 Shader operations per cycle across the entire shader array
o Shader performance: 48 billion (48,000 million) shader operations per second
* 16 Filtered & 16 unfiltered texture samples per clock
* Maximum polygon performance: 500 million triangles per second
* Pixel fillrate: 16 gigasamples per second fillrate using 4X MSAA
* Dot product operations: 9.6 billion per second theoretical
maximum, 33.6 billion per second theoretical maximum when summed with CPU operations.
* 512 MiB 700 MHz GDDR3 RAM (Total system memory is shared with the GPU via the unified memory architecture.)
The system bandwidth comprises:
* 22.4 GB/s memory interface bus bandwidth (700 MHz ? 2 accesses per clock cycle (one per edge) on a 128 bit bus)
* 256 GB/s eDRAM internal logic to eDRAM internal memory bandwidth
* 32 GB/s GPU to eDRAM bandwidth (2 GHz ? 2 accesses per clock cycle on a 64 bit DDR bus)
* 21.6 GB/s front side bus (aggregated 10.8 GB/s upstream and downstream)
* 1 GB/s southbridge bandwidth (aggregated 500 MB/s upstream and downstream)